The present invention relates to semiconductor devices and process for fabrication of the same and has for its object to provide a process for fabrication of semiconductor devices which includes a melt-flow step for forming a SiO.sub.2 layer (PSG layer) containing phosphor over the surface of a semiconductor device (such as MOSLSI) and subjecting the wafer to a heat treatment so as to obtain the flat and smooth surface and which may attain high yields in the fabrication of semiconductor devices with a high source-drain breakdown voltage and a minimal leakage current.
The melt-flow process has been proposed so as to avoid mechanical damage to aluminum metallized patterns. For instance, over the surface of a p-type wafer are formed a SiO.sub.2 layer of a thickness of about 0.8 micrometer, a source region, a drain region, a SiO.sub.2 gate film, a polysilicon gate layer and a polysilicon interconnection pattern film. Thereafter a SiO.sub.2 (PSG) layer containing phosphorus is deposited to a thickness of about 1.5 micrometer, and source, drain and gate contact windows are opened. Next the wafer is subjected to a heat treatment at about 1000.degree. C. for 30 minutes in an atmosphere of wet oxygen so that the SiO.sub.2 layers may be fluidized or melted and a layer may be deposited by thermal oxidation to a thickness of about 0.2 micrometer over the exposed surfaces of the source and drain regions and the surface of the polysilicon gate. Thereafter the wafer is placed in an etchant containing HF so as to remove the thermally oxidized films in the cntact windows and then an aluminum interconnection pattern film is deposited.
The prior art process for the fabrication of semiconductors of the type described has however some problems. That is, in the step of removing the thermally oxidized film, the etchant attacks the SiO.sub.2 (PSG) layer containing phosphorus five to 10 times as fast as it does the thermally oxidized layer so that the SiO.sub.2 (PSG) layer becomes too thin. As a consequence, pin holes are produced, and short-circuits occur between the polysilicon layer and the aluminum layer.